Print This Page

Preliminary Technical Programme

Back to Overview

Day 1 - Wednesday 24th
Day 2 - Thursday 25th
Day 3 - Friday 26th

PhD Forum

Wednesday 24th
08:00Registration Opens / Coffee
09:15 - 09:55 Keynote: "Computing Platform Requirements for Future Mobile Devices"
Yrjö Neuvo, Senior Vice President, Nokia, Finland
5 minTransition Break
Track 1.A Embedded Soft Processors
Session 10:00 1.A.1 ''CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools''
1 R. Dimond, O. Mencer, and W. Luk
Imperial College London, UK
10:00 10:25 1.A.2 ''A Reconfigurable Instruction Memory Hierarchy for Embedded Systems''
- Z. Ge, H.B. Lim, and W.F. Wong
11:15 National University of Singapore, Singapore
10:50 1.A.3 ''Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor''
M. Lanuzza¹, S. Perri¹, M. Margala², and P. Corsonello¹
¹University of Calabria, Italy, ²University of Rochester, USA
Track 1.B Logic Synthesis
10:00 1.B.1 ''FPGA PLB Evaluation using Quantified Boolean Satisfiability''
A.C. Ling¹, D.P. Singh², and S.D. Brown²
¹University of Toronto, Canada, ²Altera Toronto, Canada
10:25 1.B.2 ''FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations''
C. Morra¹, J. Becker¹, M. Ayala-Rincon², and R. Hartenstein³
¹Univ. of Karlsruhe, Germany, ²Univ. of Brasilia, Brasilia, ³Tech. Univ. of Kaiserslautern, Germany
10:50 1.B.3 ''Post-Placement BDD-Based Decomposition for FPGAs''
V. Manohararajah, D.P. Singh, and S.D. Brown
Altera Toronto, Canada
Track 1.C Networking Applications 1
10:00 1.C.1 ''Hashing + Memory = Low Cost, Exact Pattern Matching''
G. Papadopoulos¹ and D. Pnevmatikatos¹²
¹Technical University of Crete, Greece, ²Foundation for Research and Technology-Hellas, Greece
10:25 1.C.2 ''High-speed and Memory Efficient TCP Stream Scanning using FPGA''
Y. Sugawara, M. Inaba, and K. Hiraki
University of Tokyo, Japan
10:50 1.C.3 ''Mutable Codesign for Embedded Protocol Processing''
T. Sproull¹, G. Brebner², and C. Neely²
¹Washington University St. Louis, USA, ²Xilinx Research Labs, USA
11:15 - 12:05 Coffee Break / Poster Session 1
Track 2.A Chip Communication Architectures
Session 12:05 2.A.1 ''Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor''
2 C.-W. Wang, N.P. Carter, R.B. Kujoth, J.J. Cook, and D.B. Gottleib
University of Illinois at Urbana-Champaign, USA
12:05 12:30 2.A.2 ''Applying the Small-World Network to Routing Structure of FPGAs''
- H. Tsukiashi¹, M. Iida¹², and T. Sueyoshi¹
12:55 ¹Kumamoto University, Japan, ²Japan Science and Technology Agency
Track 2.B CAD for Coarse-Grained Logic
12:05 2.B.1 ''MILP-based Placement and Routing for Dataflow Architecture''
M. Healy, M. Ekpanyapong, and S.K. Lim
Georgia Institute of Technology, USA
12:30 2.B.2 ''Using DSP Blocks for ROM Replacement: A Novel Synthesis Flow''
G.W. Morris, G.A. Constantinides, and P.Y.K. Cheung
Imperial College London, UK
Track 2.C SAT Solvers and Neural Networks
12:05 2.C.1 ''An FPGA Solver for WSAT Algorithms''
K. Kanazawa and T. Maruyama
University of Tsukuba, Japan
12:30 2.C.2 ''An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning''
P.O. Domingos, F.M. Silva, and H.C. Neto
IST/INESC-ID, Portugal
12:55 - 14:25 Lunch
Track 3.A Chip Architectures
Session 14:25 3.A.1 ''Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC''
3 M. Holland and S. Hauck
Washington University Seattle, USA
14:25 14:50 3.A.2 ''A 11 GHz FPGA with Test Applications''
- C. You¹, J.-R. Guo¹, M. Chu¹, K. Zhou¹, R.P. Kraft¹, J.F. McDonald¹, and B. Goda²
15:40 ¹Rensselaer Polytechnic Institute, USA, ²US Military Academy, USA
15:15 3.A.3 ''Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes''
F.-J. Veredas¹², M. Scheppler¹, W. Moffat³, and B. Mei³
¹Infineon Technologies, Germany, ²University of Ulm, Germany, ³IMEC, Belgium
Track 3.B Arithmetic
14:25 3.B.1 ''Power and Area Optimization for Multiple Restricted Multiplication''
N. Sidahao, G.A. Constantinides, and P.Y.K. Cheung
Imperial College London, UK
14:50 3.B.2 ''Programmable Numerical Function Generators: Architectures and Synthesis Method''
T. Sasao¹, S. Nagayama², and J.T. Butler³
¹Kyushu Institute of Technology, Japan, ²FAIS, Japan, ³Naval Postgraduate School, USA
15:15 3.B.3 ''Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic''
C.T. Ewe, P.Y.K. Cheung, and G.A. Constantinides
Imperial College London, UK
Track 3.C Video Processing Applications 1
14:25 3.C.1 ''Real-time Handel-C Based Implementation of DV Decoder''
M. Gorgon, S. Cichon, and M. Pac
AGH University of Science and Technology, Poland
14:50 3.C.2 ''Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems''
N. Lawal, B. Thörnberg, and M. O'Nils
Mid Sweden University
15:15 3.C.3 ''Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing''
S.A. Fahmy, P.Y.K. Cheung, and W. Luk
Imperial College London, UK
15:40 - 16:30 Coffee Break / Poster Session 2
Track 4.A Run-Time Reconfigurable Architectures and Applications
Session 16:30 4.A.1 ''A Dynamically Reconfigurable Bluetooth Base Band Unit''
4 J. Esquiagola, G. Ozari, M. Teruya, M. Strum, and W. Chau
University of Sao Paulo, Brazil
16:30 16:55 4.A.2 ''DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices''
- C. Bobda¹, A. Ahmadinia¹, M. Majer¹, J. Teich¹, S.P. Fekete², and J. van der Veen²
17:20/17:45 ¹University of Erlangen-Nuremberg, Germany, ²Braunschweig University of Technology, Germany
Track 4.B Routing Characterization
16:30 4.B.1 ''Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks''
A. Ye and J. Rose
University of Toronto, Canada
16:55 4.B.2 ''Timing Aware Interconnect Prediction Models for FPGAs''
S. Balachandran and D. Bhatia
University of Texas at Dallas, USA
Track 4.C Multidimensional Processing
16:30 4.C.1 ''Multidimensional Dynamic Programming for Homology Search''
S. Masuno¹, T. Maruyama¹, Y. Yamaguchi¹, and A. Konagaya²
¹University of Tsukuba, Japan, ²RIKEN Genomic Sciences Center, Japan
16:55 4.C.2 ''Real-time Generation of Three-Dimensional Motion Fields''
H. Niitsuma and T. Maruyama
University of Tsukuba, Japan
17:20 4.C.3 ''Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures''
T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel, U. Kanus, and W. Straßer
Universität Tübingen, Germany
17:45 - 19:00 Informal reception, restaurat Fuuga, Tampere Hall

Thursday 25th
08:00Registration Opens / Coffee
09:00 - 09:40 Keynote: Misha Burich, Senior Vice President, Altera, USA
5 minTransition Break
Track 5.A Network on Chip Architectures
Session 09:45 5.A.1 ''A Flexible Circuit-Switched NOC for FPGA-Based Systems''
5 C. Hilton and B. Nelson
Brigham Young University, USA
09:45 10:10 5.A.2 ''Energy-Efficient NoC for Best-Effort Communication''
- P.T. Wolkotte¹, G.J.M. Smit¹, and J.E. Becker²
11:00 ¹University of Twente, The Netherlands, ²University of Karlsruhe, Germany
10:35 5.A.3 ''Fault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip Circuits''
H. Kariniemi and J. Nurmi
Tampere University of Technology, Finland
Track 5.B Tools and Methods for Run-Time Reconfiguration
09:45 5.B.1 ''Modular Partial Reconfiguration in Virtex FPGAs''
P. Sedcole¹, B. Blodget², T. Becker³, J. Anderson², and P. Lysaght²
¹Imperial College London, UK, ²Xilinx Research Labs, USA, ³University of Karlsruhe, Germany
10:10 5.B.2 ''Configuration Merging for Adaptive Computer Applications''
N. Kasprzyk¹, J.C. van der Veen¹, and A. Koch²
¹Techical University of Braunschweig, Germany, ²Technical University of Darmstadt, Germany
10:35 5.B.3 ''Context Saving and Restoring for Multitasking in Reconfigurable Systems''
H. Kalte¹ and M. Porrmann²
¹University of Western Australia, ²University of Paderborn, Germany
Track 5.C Implementation Techniques
09:45 5.C.1 ''An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate''
D. Suvakovic and I. Hadzic
Bell Labs, USA
10:10 5.C.2 ''FPGA-Based Implementation and Comparison of Recursive and Iterative Algorithms''
V. Sklyarov, I. Skliarova, and B. Pimentel
University of Aveiro, Portugal
10:35 5.C.3 ''Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA''
M. Bautista-Palacios¹, L. Baldez¹, J. Sempere-Agulló¹², A. Herms-Berenguer², F. Cardells-Tormo¹, and P.-L. Molinet¹
¹HP R&D, Spain, ²University of Barcelona, Spain
11:00 - 11:50 Coffee Break / PhD Forum
Track 6.A Defect Tolerance
Session 11:50 6.A.1 ''Defect Tolerance in Multiple-FPGA Systems''
6 Z. Hyder and J. Wawrzynek
University of California at Berkeley, USA
11:50 12:15 6.A.2 ''Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement''
- A.J. Yu and G.G.F. Lemieux
12:40 University of British Columbia, Canada
Track 6.B Compilation Methods 1
11:50 6.B.1 ''Heterogeneity Exploration for Multiple 2D Filter Designs''
C.-S. Bouganis, P.Y.K. Cheung, and G.A. Constantinides
Imperial College London, UK
12:15 6.B.2 ''Highly Automated FPGA Synthesis of Application-Specific Protocol Processors''
S. Virtanen¹, D. Truscan², J. Paakkulainen¹, J. Isoaho¹, and J. Lilius²
¹University of Turku, Finland, ²Åbo Akademi University, Finland
Track 6.C Cryptography Applications
11:50 6.C.1 ''Ziggurat-based Hardware Gaussian Random Number Generator''
G. Zhang¹, P.H.W. Leong¹, D.-U Lee², J.D. Villasenor², R.C.C. Cheung³, and W. Luk³
¹The Chinese University of Hong Kong, China, ²UCLA, USA, ³Imperial College London, UK
12:15 6.C.2 ''Snow 2.0 IP Core for Trusted Hardware''
W.H. Fang, T. Johansson, and L. Spaanenburg
Lund University, Sweden
12:40 - 14:10 Lunch
Track 7.A Asynchronous Architectures
Session 14:10 7.A.1 ''GALS Systems Prototyping using Multiclock FPGAs and Asynchronous Network-on-Chips''
7 J. Quartana, S. Renane, A. Baixas, L. Fesquet, and M. Renaudin
TIMA Laboratory, France
14:10 14:35 7.A.2 ''A Programmable Logic Architecture for Prototyping Clockless Circuits''
- L. Fesquet and M. Renaudin
15:25 TIMA Laboratory, France
15:00 7.A.3 ''A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation''
X. Jia and R. Vemuri
University of Cincinnati, USA
Track 7.B Compilation Methods 2
14:10 7.B.1 ''A Verilog RTL Synthesis Tool for Heterogeneous FPGAs''
P. Jamieson and J. Rose
University of Toronto, Canada
14:35 7.B.2 ''Compilation and Management of Phase-Optimized Reconfigurable Systems''
H. Styles and W. Luk
Imperial College London, UK
15:00 7.B.3 ''Trident: An FPGA Compiler Framework for Floating-Point Algorithms''
J.L. Tripp, K.D. Peterson, C. Ahrens, J.D. Poznanovic, and M. Gokhale
Los Alamos National Laboratory, USA
Track 7.C Bio-Inspired Computing
14:10 7.C.1 ''FPGA-Accelerated Bayesian Learning for Reconstruction of Gene Regulatory Networks''
I. Pournara¹, C.-S. Bouganis², and G.A. Constantinides²
¹Birkbeck College London, UK, ²Imperial College London, UK
14:35 7.C.2 ''Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata''
P. Zipf¹, O. Soffke¹, A. Schumacher¹, R. Dogaru², and M. Glesner¹
¹Darmstadt University of Technology, Germany, ²Polytechnic University of Bucharest, Romania
15:00 7.C.3 ''A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata''
P. Zipf¹, O. Soffke¹, A. Schumacher¹, C. Schlachta¹, R. Dogaru², and M. Glesner¹
¹Darmstadt University of Technology, Germany, ²Polytechnic University of Bucharest, Romania
15:25 - 16:05 Coffee Break / PhD Forum
Track 8.A System Architecture Exploration and Evaluation
Session 16:05 8.A.1 ''Generation and Exploration of Reconfigurable Architectures using Mathematical Programming''
8 A.M. Smith, G.A. Constantinides, and P.Y.K. Cheung
Imperial College London, UK
16:05 16:30 8.A.2 ''An I/O mechanism on a Dynamically Reconfigurable Processor -Which should be moved: Data or Configuration?''
- H. Amano, S. Abe, K. Deguchi, and Y. Hasegawa
17:20 Keio University, Japan
16:55 8.A.3 ''Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication''
M. Saito, H. Fujisawa, N. Ujiie, and H. Yoshizawa
Fujitsu Ltd., Japan
Track 8.B Communication Synthesis and High Level Design
16:05 8.B.1 ''Communication Synthesis in a Multiprocessor Environment''
C. Zissulescu, B. Kienhuis, and E. Deprettere
Leiden University, The Netherlands
16:30 8.B.2 ''PGR : A Software Package for Reconfigurable Super-Computing''
T. Hamada and N. Nakasato
The Physical and Chemical Research Institute, Japan
16:55 8.B.3 ''On-Chip Communication Topology Synthesis for Shared Multi-Bus Based Architecture''
S. Pandey, M. Glesner, and M. Mühlhäuser
Darmstadt University of Technology, Germany
Track 8.C MPEG Applications
16:05 8.C.1 ''A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC''
O. Lehtoranta, E. Salminen, A. Kulmala, M. Hännikäinen, and T.D. Hämäläinen
Tampere University of Technology, Finland
16:30 8.C.2 ''Configurable Hardware Implementation of a Conceptual Decoder for a Real-Time MPEG-2 Analysis''
M. Janiaut, C. Tanougast, H. Rabah, Y. Berviller, C. Mannino, and S. Weber
UHP, France
16:55 8.C.3 ''Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs''
K. Denolf¹, A. Chirila-Rus¹, R. Turney², P. Schumacher², and K. Vissers²
¹IMEC, Belgium, ²Xilinx Research Labs, USA
5min Transition Break
17:25 Coaches to hotels
18:10 Coaches from hotels and Tampere hall to the lake harbour
18:30 Lake cruise to Banquet
19:30 Banquet at Hotel Rosendahl

Friday 26th
08:00 Registration Opens / Coffee
Tutorials Recent Progress in FPGAs, Peter Alfke, Xilinx, USA
9:00 - 9:30 High-Speed Board Design Considerations for FPGAs, Bob Blake, Altera, UK
5 minTransition Break
Track 9.A Fault Tolerant Architectures and Systems
Session 09:35 9.A.1 ''An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation''
9 C. López-Ongil, M. García-Valderas, M. Portela-García, and L. Entrena-Arrontes
Carlos III University of Madrid, Spain
09:35 10:00 9.A.2 ''On the Reliability Evaluation of SRAM-Based FPGA Designs''
- O. Héron, T. Arnaout, and H.-J. Wunderlich
10:50 University of Stuttgart, Germany
10:25 9.A.3 ''Yield Modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes''
N. Campregher¹, P.Y.K. Cheung¹, G.A. Constantinides¹, and M. Vasilko²
¹Imperial College London, UK, ²Bournemouth University, UK
Track 9.B Placement
09:35 9.B.1 ''Fast FPGA Placement using Space-filling Curve''
P. Banerjee, S. Bhattacharjee, S. Sur-Kolay, S. Das, and S.C. Nandy
Indian Statistical Institute, India
10:00 9.B.2 ''Hierarchical Placement for Large-scale FPAA''
I.F. Baskaya, S. Reddy, S.K. Lim, and D. Anderson
Georgia Institute of Technology, USA
10:25 9.B.3 ''Architecture-Adaptive Routability-Driven Placement for FPGAs''
A. Sharma, C. Ebeling, and S. Hauck
Washington University Seattle, USA
Track 9.C Security Attacks and Detection
09:35 9.C.1 ''Generalizing Square Attack using Side-Channels of an AES Implementation on an FPGA''
V. Carlier, H. Chabanne, E. Dottax, and H. Pelletier
SAGEM SA, France
10:00 9.C.2 ''Real-Time Feature Extraction for High Speed Networks''
D. Nguyen, G. Memik, S. Ogrenci Memik, and A. Choudhary
Northwestern University, USA
10:25 9.C.3 ''Bitwise Optimised CAM for Network Intrusion Detection Systems''
S. Yusuf and W. Luk
Imperial College London, UK
10:50 - 11:40 Coffee Break / Poster Session 3
Track 10.A Video Processing Architectures and Systems
Session 11:40 10.A.1 ''High Speed / Low Power Architectures for the Finite Radon Transform''
10 S. Chandrasekaran and A. Amira
Queen's University Belfast, Northern Ireland
11:40 12:05 10.A.2 ''Towards a Reconfigurable Tracking System''
- S. Wong¹², M. Jasiunas², and D. Kearney²
12:55 ¹Defence Science and Technology Organisation, Australia, ²University of South Australia
12:30 10.A.3 ''High Performance Stereo Computation Architecture''
J. Díaz, E. Ros, S. Mota, E.M. Ortigosa, and B. del Pino
University of Granada, Spain
Track 10.B Emulation and Simulation
11:40 10.B.1 ''An Emulation Model for Sequential ATPG-Based Bounded Model Checking''
Q. Qiang¹, D.G. Saab¹, F. Kocan², and J.A. Abraham³
¹Case Western Reserve University, USA, ²Southern Methodist University, USA, ³University of Texas at Austin, USA
12:05 10.B.2 ''Accelerating Molecular Dynamics Simulations With Configurable Circuits''
Y. Gu, T. VanCourt, and M.C. Herbordt
Boston University, USA
12:30 10.B.3 ''A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits''
V. Gonçalves, J.T. de Sousa, and F. Gonçalves
IST/INESC-ID, Portugal
Track 10.C Networking Applications 2
11:40 10.C.1 ''An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding''
K. Ravindran, N. Satish, Y. Jin, and K. Keutzer
University of California at Berkeley, USA
12:05 10.C.2 ''Snort Offloader: A Reconfigurable Hardware NIDS Filter''
H. Song, T. Sproull, M. Attig, and J. Lockwood
Washington University St. Louis, USA
12:30 10.C.3 ''HAIL: A Hardware-Accelerated Algorithm for Language Identification''
C.M. Kastner, G.A. Covington, A.A. Levine, and J.W. Lockwood
Washington University St. Louis, USA
13:00Conference Close