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Preliminary Schedule

Full Papers
Tutorials
Posters
PhD Forum


Monday 22nd and Tuesday 23rd
09:00 Xilinx Professors' Worshop The DSP for FPGA Primer
16:00 At Tampere University of Technology. Register here


Wednesday 24th
08:00 Registration Opens / Coffee
09:00 Welcome
09:15 - 09:55 Keynote: "Computing Platform Requirements for Future Mobile Devices"
5min Transition Break
10:00 - 11:15 1.A Embedded Soft Processors
1.B Logic Synthesis
1.C Networking Applications 1
50min Coffee Break / Poster Session 1
12:05 - 12:55 2.A Chip Communication Architectures
2.B CAD for Coarse-Grained Logic
2.C SAT Solvers and Neural Networks
1h30m Lunch
14:25 - 15:40 3.A Chip Architectures
3.B Arithmetic
3.C Video Processing Applications 1
50min Coffee Break / Poster Session 2
16:30 - 17:20 4.A Run-Time Reconfigurable Architectures and Applications
4.B Routing Characterization
Track C-17:45 4.C Multidimensional Processing
17:45 - 19:00 Informal reception, restaurat Fuuga, Tampere Hall



Thursday 25th
08:00 Registration Opens / Coffee
09:00 - 09:40 Keynote: Misha Burich, Senior Vice President, Altera, USA
5min Transition Break
09:45 - 11:00 5.A Network on Chip Architectures
5.B Tools and Methods for Run-Time Reconfiguration
5.C Implementation Techniques
50min Coffee Break / PhD Forum
11:50 - 12:40 6.A Defect Tolerance
6.B Compilation Methods 1
6.C Cryptography Applications
1h30m Lunch
14:10 - 15:25 7.A Asynchronous Architectures
7.B Compilation Methods 2
7.C Bio-Inspired Computing
40min Coffee Break / PhD Forum
16:05 - 17:20 8.A System Architecture Exploration and Evaluation
8.B Communication Synthesis and High Level Design
8.C MPEG Applications
5min Transition Break
17:25 Coaches to hotels
18:10 Coaches from hotels and Tampere hall to the lake harbour
18:30 Lake cruise to Banquet
19:30 Banquet at Hotel Rosendahl



Friday 26th
08:00 Registration Opens / Coffee
09:00 - 09:30 Tutorials
5min Transition Break
09:35 - 10:50 9.A Fault Tolerant Architectures and Systems
9.B Placement
9.C Security Attacks and Detection
50min Coffee Break / Poster Session 3
11:40 - 12:55 10.A Video Processing Architectures and Systems
10.B Emulation and Simulation
10.C Networking Applications 2
13:00 Conference Close

Contact

Program Co-Chair
Tero Rissa
Imperial College, UK
fpl-prog-tero@cs.tut.fi