Print This Page

Posters

Back to Overview

Session 1 - 11:15 Wednesday 24th
Session 2 - 15:40 Wednesday 24th
Session 3 - 10:50 Friday 26th


Wednesday 24th
Poster Session 1
11:15 1.P.1 ''A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test''
- R. Siripokarpirom
12:05 Technical University Hamburg, Germany
1.P.2 ''A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding''
S. Yalcin, H.F. Ates, and I. Hamzaoglu
Sabanci University, Turkey
1.P.3 ''Statistical Power Estimation for FPGAs''
E. Todorovich¹, F. Angarita², J. Valls², and E. Boemo¹
¹Universidad Autónoma de Madrid, Spain, ²Universidad Politécnica de Valencia, Spain
1.P.4 ''CPU-independent Assembler in an FPGA''
G. Acher¹, R. Buchty², and C. Trinitis¹
¹Technical University of München, Germany, ²University of Karlsruhe, Germany
1.P.5 ''Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System''
C. Leong¹, P. Bento¹, P. Rodrigues², A. Trindade², J.C. Silva², P. Lousã³, J. Rego³, J. Nobre³, J. Varela², J.P. Teixeira¹, and I.C. Teixeira¹
¹INESC-ID, Portugal, ²LIP-Lisboa, Portugal, ³INOV, Portugal
1.P.6 ''Dynamic Reconfiguration with Hardwired Networks-on-Chip on Future FPGAs''
R. Hecht, S. Kubisch, A. Herrholtz, and D. Timmermann
University of Rostock, Germany
1.P.7 ''Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks''
A. García¹, J. Ramírez¹, U. Meyer-Baese², E. Castillo¹, and A. Lloris¹
¹University of Granada, Spain, ²Florida State University, USA
1.P.8 ''Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates''
F. Angarita, A. Perez-Pascual, T. Sansaloni, and J. Valls
Universidad Politécnica de Valencia, Spain
1.P.9 ''Efficient Hardware Architectures for Modular Multiplication on FPGAs''
D.N. Amanor¹³, V. Bunimov², C. Paar¹, J. Pelzl¹, and M. Schimmler²
¹Ruhr University of Bochum, Germany, ²University of Kiel, Germany, ³University of Applied Sciences, Germany
1.P.10 ''Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes''
J. Khan and R. Vemuri
University of Cincinnati, USA
1.P.11 ''FPGA Implementation of an Area-Time Efficient FIR Filter Core using a Self-Clocked Approach''
J.J. Martínez, F.J. Toledo, F.J. Garrigós, and J.M. Ferrández
Universidad Politecnica de Cartagena, Spain
1.P.12 ''Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs''
A. Schiefer and U. Kebschull
Leipzig University, Germany
1.P.13 ''QPF: Efficient Quadratic Placement for FPGAs''
Y. Xu and M.A.S. Khalid
University of Windsor, Canada
1.P.14 ''Safe PLD-based Programmable Controllers''
J. Alvarez¹, J. Marcos¹, and S. Fernandez²
¹University of Vigo, Spain, ²ATI Research Silicon Valley, USA
1.P.15 ''Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures''
J. Noguera¹ and R.M. Badia²
¹HP R&D, Spain, ²Technical University of Catalonia, Spain


Wednesday 24th
Poster Session 2
15:40 2.P.1 ''A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware''
- K. Danne and M. Platzner
16:30 University of Paderborn, Germany
2.P.2 ''A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA''
Y. Osana¹, Y. Iwaoka¹, T. Fukushima¹, M. Yoshimi¹, A. Funahashi², N. Hiroi², Y. Shibata³, N. Iwanaga³, H. Kitano², and H. Amano¹
¹Keio University, Japan, ²Japan Science and Technology Agency, ³Nagasaki University, Japan
2.P.3 ''Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing''
F. Cardells-Tormo, P.-L. Molinet, J. Sempere-Agulló, L. Baldez, and M. Bautista-Palacios
HP R&D, Spain
2.P.4 ''Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor''
M.J. Pearson, C. Melhuish, A.G. Pipe, M. Nibouche, I. Gilhesphy, K. Gurney, and B. Mitchinson
University of the West of England, UK
2.P.5 ''Evaluation Strategies for Coarse Grained Reconfigurable Architectures''
H. Lange and H. Schröder
University of Dortmund, Germany
2.P.6 ''Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration''
K. Nasi¹, M. Danek², T. Karoubalis¹, and Z. Pohl²
¹Atmel, Greece, ²Czech Academy of Sciences, Czech Republic
2.P.7 ''FPGA Implementation of a GF(2^(4m)) Multiplier for use in Pairing Based Cryptosystems''
M. Keller, T. Kerins, and W. Marnane
University College Cork, Ireland
2.P.8 ''FPGA's Middleware for Software Defined Radio Applications''
X. Revés, V. Marojevic, R. Ferrús, and A. Gelonch
Technical University of Catalonia, Spain
2.P.9 ''Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices''
D. Milojevic
Université Libre de Bruxelles, Belgium
2.P.10 ''Integration of a NoC-Based Multimedia Processing Platform''
T. Ahonen and J. Nurmi
Tampere University of Technology, Finland
2.P.11 ''LAMP: A Tool Suite for Families of FPGA-Based Computational Accelerators''
T. VanCourt and M.C. Herbordt
Boston University, USA
2.P.12 ''Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications''
S. Baloch¹², I. Ahmed¹², T. Arslan¹², and A. Stoica²³
¹Institute for System Level Integration, Scotland, ²University of Edinburgh, Scotland
2.P.13 ''Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture''
B. Mei¹, F.-J. Veredas²³, and B. Masschelein¹
¹IMEC, Belgium, ²Infineon Technologies, Belgium, ³University of Ulm, Germany
2.P.14 ''Parameterized Logic Power Consumption Models for FPGA based Arithmetic''
J.A. Clarke, A.A. Gaffar, and G.A. Constantinides
Imperial College London, UK
2.P.15 ''Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs''
G. Dimitroulakos, M.D. Galanis, and C.E. Goutis
University of Patras, Greece


Friday 26th
Poster Session 3
10:50 3.P.1 ''A Configuration Memory Architecture for Fast Run-Time Reconfiguration of FPGAs''
- U. Malik and O. Diessel
11:40 University of New South Wales, Australia
3.P.2 ''A Novel Toolset for the Development of FPGA-like Reconfigurable Logic''
A. Danilin, M. Bennebroek, and S. Sawitzki
Philips Research Labs, The Netherlands
3.P.3 ''A Reconfigurable Perfect-Hashing Scheme for Packet Inspection''
I. Sourdis¹, D. Pnevmatikatos², S. Wong¹, and S. Vassiliadis¹
¹Delft University of Technology, The Netherlands, ²Technical University of Crete, Greece
3.P.4 ''An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications''
Y. Qu¹, J.-P. Soininen¹, and J. Nurmi²
¹VTT Electronics, Finland, ²Tampere University of Technology, Finland
3.P.5 ''An FPGA Network Architecture for Accelerating 3DES - CBC''
C.M. Wee, P.R. Sutton, and N.W. Bergmann
The University of Queensland, Brisbane, Australia
3.P.6 ''An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform''
K. Siozios, K. Tatas, G. Koutroumpezis, D. Soudris, and A. Thanailakis
Democritus University of Thrace, Greece
3.P.7 ''Coping With Uncertainty in FPGA Architecture Design''
B. Ratchev, M. Hutton, and D. Mendel
Altera Inc., USA
3.P.8 ''Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA''
N. Iwanaga¹, Y. Shibata¹, M. Yoshimi², Y. Osana², Y. Iwaoka², T. Fukushima², H. Amano², A. Funahashi³, N. Hiroi³, H. Kitano³, and K. Oguri¹
¹Nagasaki University, Japan, ²Keio University, Japan, ³Japan Science and Technology Agency
3.P.9 ''Finite Field Division Implementation''
J.-P. Deschamps¹ and G. Sutter²
¹University Rovira i Virgili, Spain, ²Universidad Autonoma de Madrid, Spain
3.P.10 ''FPGA-Aware Garbage Collection in Java''
P. Faes, M. Christiaens, D. Buytaert, and D. Stroobandt
Ghent University, Belgium
3.P.11 ''High-Throughput Reconfigurable Computing: Design and Implementation of an IDEA Encryption Cryptosystem on the SRC-6E Reconfigurable Computer''
A. Michalski¹, K. Gaj², and D. Buell¹
¹University of South Carolina, USA, ²George Mason University, USA
3.P.12 ''Magnetic Remanent Memory Structures for Dynamically Reconfigurable FPGA''
N. Bruchon, G. Cambon, L. Torres, and G. Sassatelli
University of Montpellier II, France
3.P.13 ''Mullet - A Parallel Multiplier Generator''
K.H. Tsoi and P.H.W. Leong
The Chinese University of Hong Kong, China
3.P.14 ''NetFlow Probe Intended for High-Speed Networks''
M. Zádník, T. Pecenka, and J. Korenek
Brno University of Technology, Czech Republic
3.P.15 ''Performance Tuning of Iterative Algorithms in Signal Processing''
Z. Pohl¹, P. Sucha², J. Kadlec¹, and Z. Hanzálek²
¹Academy of Sciences of the Czech Republic, ²Czech Technical University in Prague
3.P.16 ''Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors''
P. Benoit¹, J. Becker¹, M. Robert², L. Torres², G. Sassatelli², and G. Cambon²
¹University of Karlsrhuhe, Germany, ²University of Montpellier II, France